国家/地区 美国（41） 中国（6） 世界知识产权组织（4）
IPC部 H（35） B（18） C（6）
G（6）
IPC大类 H01（34） B82（14） C01（5）
G01（5） B32（4） C25（2）
H03（2） H05（2）
IPC小类 H01L（33） B82Y（14） C01B（5）
B32B（4） G01N（4） C25F（2）
H01B（2） H03B（2） H05K（2）
IPC H01L029/66（11） B82Y040/00（10） H01L029/06（9）
H01L029/78（9） H01L021/02（8） H01L029/16（8）
B82Y099/00（6） H01L021/336（6） H01L023/532（5）
B82Y010/00（4） C01B031/04（4） H01L021/20（4）
H01L021/28（4） H01L021/768（4） H01L029/786（4）
发明人 DIMITRAKOPOULOS C D（10） SMITH J T（8） FRANKLIN A D（6）
HAN S（6） AFZALIARDAKANI A（5） FARMER D B（5）
LIN Y（5） OIDA S（5） PFEIFFER D（5）
BONILLA G（4） GRILL A（4） HANNON J B（4）
BAO J（3） CHOI S S（3） FILIPPI R G（3）
公开年 2014（41）
申请年 2013（19）  2012（18）  2014（4） 
专利权人 INT BUSINESS MACHINES CORP（41）

Device structure e.g. graphene device structure has spaced apart contact with portion on metal layer and insulating substrate, first patterned carbon-based nanostructure layer with regions are not covered by first patterned metal layer.

CHU J O, DIMITRAKOPOULOS C D, GRILL A, MCARDLE T J, PFEIFFER D, SAENGER K L, WISNIEFF R L

Structure e.g. microelectronic interconnect structures for hybrid graphene-metal lines, has secondary level with secondary level metal and via that electrically connects third metal to secondary level metal in vertical orientation.

BAO J, BONILLA G, CHOI S S, FILIPPI R G, KIM A T, LUSTIG N E, SIMON A H

Solid-state device structure for separating and isolating graphene monolayer, has single crystalline monolayer of graphene that is arranged on substrate by single transfer process and has surface area of greater than specific inches.

DIMITRAKOPOULOS C D, FOGEL K E, KIM J, PARK H

Interconnect structure e.g. hybrid graphene-metal interconnect structure has conductive line with graphene portions and line barrier layers surrounds each graphene portions, line barrier layer has barrier and graphene seed material.

BAO J, BONILLA G, CHOI S S, FILIPPI R G, LUSTIG N E, SIMON A H

Carbon nanotube manufacturing method e.g. for nanotube-based transistor, involves aligning carbon nanotubes between graphene electrodes in direction parallel with electric field generated across graphene electrodes.

AVOURIS P, DIMITRAKOPOULOS C, FARMER D B, STEINER M B, ENGEL M, KRUPKE R, LIN Y

Method for transferring graphene to wafer in semiconductor device for microelectronics application, involves exfoliating closest monolayer by mechanically splitting spreading layer in which closest monolayer remains on stressor layer.

BEDELL S W, DIMITRAKOPOULOS C D, FOGEL K E, HANNON J B, KIM J, PARK H, PFEIFFER D, SADANA D K, SALDANHA D K, PARK H S

Graphene nanomesh used in e.g. nanoelectronics comprises graphene sheet having pores with first diameter; and several passivation elements bonded to inner edge of pore, where elements have second diameter that is less than first diameter.

AFZALIARDAKANI A, MAAROUF A A, MARTYNA G J

Forming pores in graphene sheet includes locating graphene sheet in vacuum containing many passivation elements e.g. styrene, forming pore having first diameter via electron-beam and exposing carbon sites to passivation elements.

AFZALIARDAKANI A, MAAROUF A A, MARTYNA G J, MAROOF A A

Back-end-of-the-line interconnect structure e.g. air-gap-containing interconnect structure for semiconductor device has graphene layer that includes first portion whose bottommost surface is in contact with surface of substrate.

OTT J A, BOL A A

Back-end-of-the line single/dual damascene graphene and metal interconnect structure for use in e.g. integrated circuit chip, has lower vertical interconnect access whose top end is connected to end of graphene connector.

BAO J, BONILLA G, CHOI S S, FILIPPI R G, LUSTIG N E, SIMON A H